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? semiconductor components industries, llc, 2013 august, 2013 ? rev. 11 1 publication order number: uc3844b/d uc3844b, uc3845b, uc2844b, uc2845b high performance current mode controllers the uc3844b, uc3845b series are high performance fixed frequency current mode controllers. they are specifically designed for off ? line and dc ? dc converter applications offering the designer a cost ? effective solution with minimal external components. these integrated circuits feature an oscillator, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power mosfet. also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle ? by ? cycle current limiting, a latch for single pulse metering, and a flip ? flop which blanks the output off every other oscillator cycle, allowing output deadtimes to be programmed from 50% to 70%. these devices are available in an 8 ? pin dual ? in ? line and surface mount (soic ? 8) plastic package as well as the 14 ? pin plastic surface mount (soic ? 14). the soic ? 14 package has separate power and ground pins for the totem pole output stage. the ucx844b has uvlo thresholds of 16v (on) and 10v (off), ideally suited for off ? line converters. the ucx845b is tailored for lower voltage applications having uvlo thresholds of 8.5v (on) and 7.6v (off). features ? trimmed oscillator for precise frequency control ? oscillator frequency guaranteed at 250 khz ? current mode operation to 500 khz output switching frequency ? output deadtime adjustable from 50% to 70% ? automatic feed forward compensation ? latching pwm for cycle ? by ? cycle current limiting ? internally trimmed reference with undervoltage lockout ? high current totem pole output ? undervoltage lockout with hysteresis ? low startup and operating current ? these devices are pb ? free and are rohs compliant ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable pin numbers in parenthesis are for the d suffix soic-14 package. output v c r t /c t v ref v cc undervoltage lockout gnd 5.0v reference v ref undervoltage lockout latching pwm oscillator error amplifier 5(9) 3(5) 5(8) 6(10) 7(11) power ground current sense input 1(1) 2(3) 4(7) 8(14) output/ compensation voltage feedback input v cc 7(12) r r figure 1. simplified block diagram 14 soic ? 14 d suffix case 751a 1 see detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. ordering information see general marking information in the device marking section on page 16 of this data sheet. device marking information 1 8 pdip ? 8 n suffix case 626 pin connections compensation nc voltage feedback nc current sense nc r t /c t compensation voltage feedback current sense r t /c t v ref v ref nc v cc v c output gnd power ground v cc output gn d (top view) 8 7 6 5 1 2 3 4 1 2 3 4 14 13 12 11 5 6 7 10 9 8 (top view) soic ? 8 d1 suffix case 751 1 8 http://onsemi.com
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 2 maximum ratings rating symbol value unit bias and driver voltages (zero series impedance, see also total device spec) (note 1) v cc , v c 36 v total power supply and zener current (i cc + i z ) 30 ma output current, source or sink (note 2) i o 1.0 a output energy (capacitive load per cycle) w 5.0 j current sense and voltage feedback inputs v in ? 0.3 to + 5.5 v error amp output sink current i o 10 ma power dissipation and thermal characteristics d suffix, plastic package, soic ? 14 case 751a maximum power dissipation @ t a = 25 c thermal resistance, junction ? to ? air d1 suffix, plastic package, soic ? 8 case 751 maximum power dissipation @ t a = 25 c thermal resistance, junction ? to ? air n suffix, plastic package, case 626 maximum power dissipation @ t a = 25 c thermal resistance, junction ? to ? air p d r ja p d r ja p d r ja 862 145 702 178 1.25 100 mw c/w mw c/w w c/w operating junction temperature t j +150 c operating ambient temperature uc3844b, uc3845b uc2844b, uc2845b uc3844bv, uc3845bv t a 0 to +70 ? 25 to +85 ? 40 to +105 c storage temperature range t stg ? 65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the voltage is clamped by a zener diode (see page 9 under voltage lockout section). therefore this voltage may be exceeded as long as the total power supply and zener current is not exceeded. 2. maximum package power dissipation limits must be observed. 3. this device series contains esd protection and exceeds th e following tests: human body model 4000 v per jedec standard jesd22-a114b, machine model method 200 v per jedec standard jesd22-a115-a 4. this device contains latch-up protection and exceeds 100 ma per jedec standard jesd78 electrical characteristics (v cc = 15 v [note 5], r t = 10 k, c t = 3.3 nf. for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies [note 6], unless otherwise noted.) uc284xb uc384xb, xbv, ncv384xbv characteristic symbol min typ max min typ max unit reference section reference output voltage (i o = 1.0 ma, t j = 25 c) v ref 4.95 5.0 5.05 4.9 5.0 5.1 v line regulation (v cc = 12 v to 25 v) reg line ? 2.0 20 ? 2.0 20 mv load regulation (i o = 1.0 ma to 20 ma) reg load ? 3.0 25 ? 3.0 25 mv temperature stability t s ? 0.2 ? ? 0.2 ? mv/ c total output variation over line, load, & temperature v ref 4.9 ? 5.1 4.82 ? 5.18 v output noise voltage (f = 10 hz to 10 khz, t j = 25 c) v n ? 50 ? ? 50 ? v long term stability (t a = 125 c for 1000 hours) s ? 5.0 ? ? 5.0 ? mv output short circuit current i sc ? 30 ? 85 ? 180 ? 30 ? 85 ? 180 ma oscillator section frequency t j = 25 c t a = t low to t high t j = 25 c (r t = 6.2 k, c t = 1.0 nf) f osc 49 48 225 52 ? 250 55 56 275 49 48 225 52 ? 250 55 56 275 khz frequency change with voltage (v cc = 12 v to 25 v) f osc / v ? 0.2 1.0 ? 0.2 1.0 % frequency change w/ temperature (t a = t low to t high ) f osc / t ? 1.0 ? ? 0.5 ? % oscillator voltage swing (peak ? to ? peak) v osc ? 1.6 ? ? 1.6 ? v 5. adjust v cc above the startup threshold before setting to 15 v. 6. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low =0 c for uc3844b, uc3845b t high =+70 c for uc3844b, uc3845b = ? 25 c for uc2844b, uc2845b = + 85 c for uc2844b, uc2845b = ? 40 c for uc384xbv, ncv384xbv =+105 c for uc3844bv, uc3845bv = +125 c for ncv384xbv
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 3 electrical characteristics (v cc = 15 v [note 7], r t = 10 k, c t = 3.3 nf. for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies [note 8], unless otherwise noted.) uc284xb uc384xb, xbv, ncv384xbv characteristic symbol min typ max min typ max unit oscillator section discharge current (v osc = 2.0 v) t j = 25 c t a = t low to t high (uc284xb, uc384xb) (uc384xbv) i dischg 7.8 7.5 ? 8.3 ? ? 8.8 8.8 ? 7.8 7.6 7.2 8.3 ? ? 8.8 8.8 8.8 ma error amplifier section voltage feedback input (v o = 2.5 v) v fb 2.45 2.5 2.55 2.42 2.5 2.58 v input bias current (v fb = 5.0 v) i ib ? ? 0.1 ? 1.0 ? ? 0.1 ? 2.0 a open loop voltage gain (v o = 2.0 v to 4.0 v) a vol 65 90 ? 65 90 ? db unity gain bandwidth (t j = 25 c) bw 0.7 1.0 ? 0.7 1.0 ? mhz power supply rejection ratio (v cc = 12 v to 25 v) psrr 60 70 ? 60 70 ? db output current ? sink (v o = 1.1 v, v fb = 2.7 v) output current ? source (v o = 5.0 v, v fb = 2.3 v) i sink i source 2.0 ? 0.5 12 ? 1.0 ? ? 2.0 ? 0.5 12 ? 1.0 ? ? ma output voltage swing high state (r l = 15 k to ground, v fb = 2.3 v) low state (r l = 15 k to v ref , v fb = 2.7 v) (uc284xb, uc384xb) (uc384xbv) v oh v ol 5.0 ? ? 6.2 0.8 ? ? 1.1 ? 5.0 ? ? 6.2 0.8 0.8 ? 1.1 1.2 v current sense section current sense input voltage gain (notes 9 & 10) (uc284xb, uc384xb) (uc384xbv) a v 2.85 ? 3.0 ? 3.15 ? 2.85 2.85 3.0 3.0 3.15 3.25 v/v maximum current sense input threshold (note 9) (uc284xb, uc384xb) (uc384xbv) v th 0.9 ? 1.0 ? 1.1 ? 0.9 0.85 1.0 1.0 1.1 1.1 v power supply rejection ratio (v cc = 12 v to 25 v) (note 9) psrr ? 70 ? ? 70 ? db input bias current i ib ? ? 2.0 ? 10 ? ? 2.0 ? 10 a propagation delay (current sense input to output) t plh(in/out) ? 150 300 ? 150 300 ns output section output voltage low state (i sink = 20 ma) (i sink = 200 ma, uc284xb, uc384xb) (i sink = 200 ma, uc384xbv) high state (i source = 20 ma, uc284xb, uc384xb) (i source = 20 ma, uc384xbv) (i source = 200 ma) v ol v oh ? ? ? 13 ? 12 0.1 1.6 ? 13.5 ? 13.4 0.4 2.2 ? ? ? ? ? ? ? 13 12.9 12 0.1 1.6 1.6 13.5 ? 13.4 0.4 2.2 2.3 ? ? ? v output voltage with uvlo activated (v cc = 6.0 v, i sink = 1.0 ma) v ol(uvlo) ? 0.1 1.1 ? 0.1 1.1 v output voltage rise time (c l = 1.0 nf, t j = 25 c) t r ? 50 150 ? 50 150 ns output voltage fall time (c l = 1.0 nf, t j = 25 c) t f ? 50 150 ? 50 150 ns undervoltage lockout section startup threshold ucx844b, bv ucx845b, bv v th 15 7.8 16 8.4 17 9.0 14.5 7.8 16 8.4 17.5 9.0 v minimum operating voltage after turn ? on ucx844b, bv ucx845b, bv v cc(min) 9.0 7.0 10 7.6 11 8.2 8.5 7.0 10 7.6 11.5 8.2 v 7. adjust v cc above the startup threshold before setting to 15 v. 8. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low =0 c for uc3844b, uc3845b t high =+70 c for uc3844b, uc3845b = ? 25 c for uc2844b, uc2845b = + 85 c for uc2844b, uc2845b = ? 40 c for uc384xbv, ncv384xbv = +105 c for uc3844bv, uc3845bv = +125 c for ncv384xbv 9. this parameter is measured at the latch trip point with v fb = 0 v. 10. comparator gain is defined as: a v = v output/compensation v current sense input
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 4 electrical characteristics (v cc = 15 v [note 11], r t = 10 k, c t = 3.3 nf. for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies [note 12], unless otherwise noted.) uc284xb uc384xb, xbv, ncv384xbv characteristic symbol min typ max min typ max unit pwm section duty cycle maximum (uc284xb, uc384xb) maximum (uc384xbv) minimum dc (max) dc (min) 47 ? ? 48 ? ? 50 ? 0 47 46 ? 48 48 ? 50 50 0 % total device power supply current startup (v cc = 6.5 v for ucx845b, startup (v cc = 14 v for ucx844b, bv) operating (note 11) i cc ? ? 0.3 12 0.5 17 ? ? 0.3 12 0.5 17 ma power supply zener voltage (i cc = 25 ma) v z 30 36 ? 30 36 ? v 11. adjust v cc above the startup threshold before setting to 15 v. 12. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. t low =0 c for uc3844b, uc3845b t high =+70 c for uc3844b, uc3845b = ? 25 c for uc2844b, uc2845b = + 85 c for uc2844b, uc2845b = ? 40 c for uc384xbv, ncv384xbv = +105 c for uc3844bv, uc3845bv =+125 c for ncv384xbv 0.8 2.0 5.0 8.0 20 50 80 r t , timing resistor (k ) 1.0 m 500 k 200 k 100 k 50 k 20 k 10 k f osc , oscillator frequency (khz) figure 2. timing resistor versus oscillator frequency figure 3. output deadtime versus oscillator frequency 1.0 m 100 k 10 k f osc , oscillator frequency (khz) 50 % dt, percent output deadtime ????? ????? ????? ????? ????? ????? c 0.5 s/div 20 mv/div 2.55 v 2.5 v 2.45 v v cc = 15 v a v = -1.0 t a = 25 c v cc = 15 v a v = -1.0 t a = 25 c 1.0 s/div 200 mv/div 2.5 v 3.0 v 2.0 v figure 4. error amp small signal transient response figure 5. error amp large signal transient response 1 4 for r t 5kf 1.72 r t c t
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 5 , output voltage change (2.0 mv/div) o v -20 a vol , open loop voltage gain (db) 10 m 10 f, frequency (hz) gain phase 0 30 60 90 120 150 180 100 1.0 k 10 k 100 k 1.0 m 0 20 40 60 80 100 , excess phase (degrees) 0 v o , error amp output voltage (v o ) 0 , current sense input threshold (v ) v th 0.2 0.4 0.6 0.8 1.0 1.2 2.0 4.0 6.0 8.0 t a = -55 c ???? ???? 0.1 figure 6. error amp open loop gain and phase versus frequency figure 7. current sense input threshold versus error amp output voltage figure 8. reference voltage change versus source current figure 9. reference short circuit current versus temperature , reference voltage change (mv) -16 0 i ref , reference source current (ma) 20 40 60 80 100 120 ref v -12 -8.0 -4.0 0 , reference short circuit current (ma) sc i 50 -55 t a , ambient temperature ( c) -25 0 25 50 75 100 125 70 90 110 -20 -24 t a = 125 c v cc = 15 v v o = 2.0 v to 4.0 v r l = 100 k t a = 25 c v cc = 15 v t a = 25 c , output voltage change (2.0 mv/div) o 2.0 ms/div v 2.0 ms/div v cc = 12 v to 25 v t a = 25 c v cc = 15 v i o = 1.0 ma to 20 ma t a = 25 c figure 10. reference load regulation figure 11. reference line regulation v cc = 15 v t a = 125 c t a = 25 c t a = -55 c
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 6 ????? ????? sink saturation (load to v cc ) ???? ???? ???? ???? c , supply current (ma) cc i 0 0 v cc , supply voltage (v) 10 20 30 40 5 10 15 20 25 ucx845b ucx844b figure 12. output saturation voltage versus load current figure 13. output waveform ??? ??? t a = 25 c ???? ???? c ?? ????? ????? s pulsed load 120 hz rate ???? ???? c ???? ???? c 0 v sat , o utput s aturati o n v o lta g e ( v ) 800 0 i o , output load current (ma) 200 400 600 1.0 2.0 3.0 -2.0 -1.0 0 ????? ????? ??? c 100 ns/div v cc = 30 v c l = 15 pf t a = 25 c , supply current 100 ma/div 20 v/div i , output voltage v cc o figure 14. output cross conduction figure 15. supply current versus supply voltage pin function description pin function description 8 ? pin 14 ? pin 1 1 compensation this pin is the error amplifier output and is made available for loop compensation. 2 3 voltage feedback this is the inverting input of the error amplifier. it is normally connected to the switching power supply output through a resistor divider. 3 5 current sense a voltage proportional to inductor current is connected to this input. the pwm uses this information to terminate the output switch conduction. 4 7 r t /c t the oscillator frequency and maximum output duty cycle are programmed by connecting resistor r t to v ref and capacitor c t to ground. oscillator operation to 1.0 khz is possible. 5 gnd this pin is the combined control circuitry and power ground. 6 10 output this output directly drives the gate of a power mosfet. peak currents up to 1.0 a are sourced and sunk by this pin. the output switches at one ? half the oscillator frequency. 7 12 v cc this pin is the positive supply of the control ic. 8 14 v ref this is the reference output. it provides charging current for capacitor c t through resistor r t . 8 power ground this pin is a separate power ground return that is connected back to the power source. it is used to reduce the effects of switching transient noise on the control circuitry. 11 v c the output high state (v oh ) is set by the voltage applied to this pin. with a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. 9 gnd this pin is the control circuitry ground return and is connected back to the powersource ground. 2,4,6,13 nc no connection. these pins are not internally connected.
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 7 operating description the uc3844b, uc3845b series are high performance, fixed frequency, current mode controllers. they are specifically designed for off ? line and dc ? dc converter applications offering the designer a cost ? effective solution with minimal external components. a representative block diagram is shown in figure 16. oscillator the oscillator frequency is programmed by the values selected for the timing components r t and c t . capacitor c t is charged from the 5.0 v reference through resistor r t to approximately 2.8 v and discharged to 1.2 v by an internal current sink. during the discharge of c t , the oscillator generates an internal blanking pulse that holds the center input of the nor gate high. this causes the output to be in a low state, thus producing a controlled amount of output deadtime. an internal flip ? flop has been incorporated in the ucx844/5b which blanks the output off every other clock cycle by holding one of the inputs of the nor gate high. this in combination with the c t discharge period yields output deadtimes programmable from 50% to 70%. figure 2 shows r t versus oscillator frequency and figure 3, output deadtime versus frequency, both for given values of c t . note that many values of r t and c t will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. the oscillator thresholds are temperature compensated to within 6% at 50 khz. also, because of industry trends moving the uc384x into higher and higher frequency applications, the uc384xb is guaranteed to within 10% at 250 khz. in many noise ? sensitive applications it may be desirable to frequency ? lock the converter to an external system clock. this can be accomplished by applying a clock signal to the circuit shown in figure 18. for reliable locking, the free ? running oscillator frequency should be set about 10% less than the clock frequency. a method for multi ? unit synchronization is shown in figure 19. by tailoring the clock waveform, accurate output duty cycle clamping can be achieved to realize output deadtimes of greater than 70%. error amplifier a fully compensated error amplifier with access to the inverting input and output is provided. it features a typical dc voltage gain of 90 db, and a unity gain bandwidth of 1.0 mhz with 57 degrees of phase margin (figure 6). the non ? inverting input is internally biased at 2.5 v and is not pinned out. the converter output voltage is typically divided down and monitored by the inverting input. the maximum input bias current is ? 2.0 a which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. the error amp output (pin 1) is provided for external loop compensation (figure 29). the output voltage is offset by two diode drops ( 1.4 v) and divided by three before it connects to the inverting input of the current sense comparator. this guarantees that no drive pulses appear at the output (pin 6) when pin 1 is at its lowest state (v ol ). this occurs when the power supply is operating and the load is removed, or at the beginning of a soft ? start interval (figures 21, 22). the error amp minimum feedback resistance is limited by the amplifier?s source current (0.5 ma) and the required output voltage (v oh ) to reach the comparator?s 1.0 v clamp level: r f(min) 3.0 (1.0 v) + 1.4 v 0.5 ma = 8800 current sense comparator and pwm latch the uc3844b, uc3845b operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the error amplifier output/compensation (pin 1). thus the error signal controls the peak inductor current on a cycle ? by ? cycle basis. the current sense comparator pwm latch configuration used ensures that only a single pulse appears at the output during any given oscillator cycle. the inductor current is converted to a voltage by inserting the ground ? referenced sense resistor r s in series with the source of output switch q1. this voltage is monitored by the current sense input (pin 3) and compared to a level derived from the error amp output. the peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: i pk = v (pin 1) ? 1.4 v 3 r s abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. under these conditions, the current sense comparator threshold will be internally clamped to 1.0 v. therefore the maximum peak switch current is: i pk(max) = 1.0 v r s when designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of r s to a reasonable level. a simple method to adjust this voltage is shown in figure 20. the two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. erratic operation due to noise pickup can result if there is an excessive reduction of the i pk(max) clamp voltage. a narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. this spike is due to the power transformer interwinding capacitance and output rectifier recovery time. the addition of an rc filter on the current sense input with a time constant that approximates the spike duration will usually eliminate the instability (refer to figure 24).
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 8 figure 16. representative block diagram figure 17. timing diagram capacitor c t latch set" input output/ compensation current sense input latch reset" input output large r t /small c t small r t /large c t + - reference regulator v cc uvlo + - v ref uvlo 3.6v 36v s r q internal bias + 1.0ma oscillator 2.5v r r r 2r error amplifier voltage feedback input output/ compensation current sense comparator 1.0v v cc 7(12) gnd 5(9) v c 7(11) output 6(10) power ground 5(8) current sense input 3(5) r s q1 v cc v in 1(1) 2(3) 4(7) 8(14) r t c t v ref = sink only positive true logic pin numbers adjacent to terminals are for the 8-pin dual-in-line package. pin numbers in parenthesis are for the d suffix soic-14 package. pwm latch (see text) t
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 9 undervoltage lockout two undervoltage lockout comparators have been incorporated to guarantee that the ic is fully functional before the output stage is enabled. the positive power supply terminal (v cc ) and the reference output (v ref ) are each monitored by separate comparators. each has built ? in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. the v cc comparator upper and lower thresholds are 16 v/10 v for the ucx844b, and 8.4 v/7.6 v for the ucx845b. the v ref comparator upper and lower thresholds are 3.6 v/3.4 v. the large hysteresis and low startup current of the ucx844b makes it ideally suited in off ? line converter applications where efficient bootstrap startup techniques are required (figure 30). the ucx845b is intended for lower voltage dc ? dc converter applications. a 36 v zener is connected as a shunt regulator from v cc to ground. its purpose is to protect the ic from excessive voltage that can occur during system startup. the minimum operating voltage for the ucx844b is 11 v and 8.2 v for the ucx845b. output these devices contain a single totem pole output stage that was specifically designed for direct drive of power mosfets. it is capable of up to 1.0 a peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nf load. additional internal circuitry has been added to keep the output in a sinking mode whenever an undervoltage lockout is active. this characteristic eliminates the need for an external pulldown resistor. the soic ? 14 surface mount package provides separate pins for v c (output supply) and power ground. proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. this becomes particularly useful when reducing the i pk(max) clamp level. the separate v c supply input allows the designer added flexibility in tailoring the drive voltage independent of v cc . a zener clamp is typically connected to this input when driving power mosfets in systems where v cc is greater than 20 v. figure 23 shows proper power and control ground connections in a current ? sensing power mosfet application. reference the 5.0 v bandgap reference is trimmed to 1.0% tolerance at t j = 25 c on the uc284xb, and 2.0% on the uc384xb. its primary purpose is to supply char ging current to the oscillator timing capacitor. the reference has short ? circuit protection and is capable of providing in excess of 20 ma for powering additional control system circuitry. design considerations do not attempt to construct the converter on wire ? wrap or plug ? in prototype boards. high frequency circuit layout techniques are imperative to prevent pulse ? width jitter. this is usually caused by ex cessive noise pick ? up imposed on the current sense or v oltage feedback inputs. noise immunity can be improved by lowering circuit impedances at these points. the printed circuit layout should contain a ground plane with low ? current signal and high ? current switch and output grounds returning on separate paths back to the input filter capacitor. ceramic bypass capacitors (0.1 f) connected directly to v cc , v c , and v ref may be required depending upon circuit layout. this provides a low impedance path for filtering the high frequency noise. all high current loops should be kept as short as possible using heavy copper runs to minimize radiated emi. the error amp compensation circuitry and the converter output voltage divider should be located close to the ic and as far as possible from the power switch and other noise ? generating components. bias + osc r r r 2r ea 5(9) 1(1) 2(3) 4(7) 8(14) r t c t v ref figure 18. external clock synchronization figure 19. external duty cycle clamp and multi ? unit synchronization 0.01 the diode clamp is required if the sync amplitude is large enough to cause the bottom side of c t to go more than 300 mv below ground. external sync input 47 + r r r 2r bias osc ea 5(9) 1(1) 2(3) 4(7) 8(14) to additional ucx84xbs r s q 8 4 6 5 2 1 c 3 7 r a r b 5.0k 5.0k 5.0k mc1455 f 1.44 (r a 2r b )c d (max) r a r a 2r b
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 10 if: sensefet = mtp10n10m r s = 200 figure 20. adjustable reduction of clamp level figure 21. soft ? start circuit figure 22. adjustable buffered reduction of clamp level with soft ? start + - 5.0v ref + - s r q bias + osc r r r 2r ea 1.0v 5(9) 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in 1(1) 2(3) 4(7) 8(14) r 1 v clamp r 2 i pk(max) v clamp r s where: 0 v clamp 1.0 v 5.0v ref + - s r q bias + 1.0ma osc r r r 2r ea 1.0v 5(9) 1(1) 2(3) 4(7) 8(14) c 1.0m t soft-start 3600c in f + - + - s r + r r r 2r i pk(max) v clamp r s figure 23. current sensing power mosfet 5.0v ref q bias osc ea 1.0v 5(9) 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in 1(1) 2(3) 4(7) 8(14) r 1 r 2 where: 0 v clamp 1.0 v mpsa63 + - 5.0v ref + - s r q (11) (10) (8) comp/latch (5) r s 1/4 w v cc v in k m d sensefet g s power ground: to input source return control circuitry ground: to pin (9) virtually lossless current sensing can be achieved with the implementation of a sensefet power switch. for proper operation during over-current conditions, a reduction of the i pk(max) clamp level must be implemented. refer to figures 20 and 22. v pin5 r s i pk r ds(on) r dm(on) r s then : v pin5 0.075i pk 7(12) 7(12) 1.0 ma comp/latch comp/latch 1.0 ma (12) t t t t v clamp v clamp 1.67 r 2 r 1 1 + 0.33x10 -3 r 1 r 2 r 1 r 2 v clamp 1.67 r 2 r 1 1 t soft start in
1 v c 3v clamp c r 1 r 2 r 1 r 2
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 11 figure 24. current waveform spike suppression + - 5.0v ref + - s r q 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in c r the addition of the rc filter will eliminate instability caused by the leading edge spike on the current waveform. 7(12) comp/latch t figure 25. mosfet parasitic oscillations figure 26. bipolar transistor drive + - s r 5.0v ref q 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in series gate resistor r g will damp any high frequency parasitic oscillations caused by the mosfet input capacitance and any series wiring inductance in the gate-source circuit. 6(10) 5(8) 3(5) r s q1 v in c1 base charge removal the totem pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor c 1 . i b + - 0 7(12) r g comp/latch t + -
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 12 + r 2r 1.0ma ea 2(3) 5(9) 2.5v 1(1) r f c f r d r p from v o error amp compensation circuit for stabilizing current mode boost and flyback topologies operating with continuous inductor current. c p r i figure 27. isolated mosfet drive figure 28. latched shutdown figure 29. error amplifier compensation + - s r 5.0v ref q 7(11) 6(10) 5(8) 3(5) r s q1 v cc v in isolation boundary v gs waveforms + - 0 50% dc 25% dc n s n p bias + osc r r r 2r ea 5(9) 1(1) 2(3) 4(7) 8(14) the mcr101 scr must be selected for a holding of < 0.5 ma @ t a(min) . the simple two transistor circuit can be used in place of the scr as shown. all resistors are 10 k. mcr 101 2n 3905 2n 3903 + r 2r 1.0ma ea 2(3) 5(9) 2.5v 1(1) r f c f r d r i from v o error amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current. r f 8.8k comp/latch 7(12) r c n s n p 1.0 ma t + - 0 + - i pk = v (pin1) - 1.4 3 r s
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 13 mur110 + - + - s r + r r 5.0v ref q bias ea 5(9) 7(11) 6(10) 5(8) 3(5) 0.5 mtp 4n50 1(1) 2(3) 4(7) 8(14) 33k 1.0nf 470pf 150k 100 pf 18k 4.7k figure 30. 7 w off ? line flyback regulator 0.01 100 + 1.0k 115 vac 4.7 mda 202 250 56k 4.7k 3300 pf 1n4935 1n4935 + + 68 47 1n4937 1n4937 680pf 2.7k l3 l2 l1 ++ ++ ++ 1000 1000 2200 10 10 1000 5.0v/4.0a 5.0v rtn 12v/0.3a 12v rtn -12v/0.3a primary: 45 turns #26 awg secondary 12 v: 9 turns #30 awg (2 strands) bifiliar wound secondary 5.0 v: 4 turns (six strands) #26 hexfiliar wound secondary feedback: 10 turns #30 awg (2 strands) bifiliar wound core: ferroxcube ec35-3c8 bobbin: ferroxcube ec35pcb1 gap: 0.10" for a primary inductance of 1.0 mh mur110 mbr1635 t1 22 osc t1 - 7(12) comp/latch t l1 l2, l3 - 15 h at 5.0 a, coilcraft z7156 - 25 h at 5.0 a, coilcraft z7157 1n5819 test conditions results line regulation: 5.0 v 12 v v in = 95 vac to 130 vac = 50 mv or 0.5% = 24 mv or 0.1% load regulation: 5.0 v 12 v v in = 115 vac, i out = 1.0 a to 4.0 a v in = 115 vac, i out = 100 ma to 300 ma = 300 mv or 3.0% = 60 mv or 0.25% output ripple: 5.0 v 12 v v in = 115 vac 40 mv pp 80 mv pp efficiency v in = 115 vac 70% all outputs are at nominal load currents unless otherwise noted.
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 14 osc + - reference regulator + - 34v s r q internal bias + 0.5ma osc r r r 2r error amplifier 1.0v 7(12) 7(11) 6(10) 5(8) 3(5) r1 v in = 15v 1(1) 2(3) 4(7) 8(14) 10k 1.0nf the capacitor's equivalent series resistance must limit the drive output current to 1.0 a. an additional series resistor may be required when using tantalum or other low esr capacitors. the converter's output can provide excellent line and load regulation by connecting the r2/r1 resistor divider as shown. figure 31. step ? up charge pump converter 5(9) pwm t latch current sense comparator 2.5v 3.6v v cc uvlo v ref uvlo uc3845b + 47 1n5819 15 10 1n5819 + 47 r2 connect to pin 2 for closed loop operation. r2 r1 1 v o 2 (v in ) output load regulation (open loop configuration) i o (ma) v o (v) 0 2 9 18 36 29.9 28.8 28.3 27.4 24.4 + - + - s r + r r r 2r 5(9) pwm t latch current sense comparator + 47 15 10 1n5819 + 47 reference regulator 34v q internal bias 0.5ma error amplifier 1.0v 7(12) 7(11) 6(10) 5(8) 3(5) v in = 15v 1(1) 2(3) 4(7) 8(14) 10k 1.0nf the capacitor's equivalent series resistance must limit the drive output current to 1.0 a. an additional series resistor may be required when using tantalum or other low esr capacitors. figure 32. voltage ? inverting charge pump converter 2.5v 3.6v v cc uvlo v ref uvlo uc3845b v o -v in output load regulation i o (ma) v o (v) 0 2 9 18 32 ? 14.4 ? 13.2 ? 12.5 ? 11.7 ? 10.6 1n5819 + v o = 2.5
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 15 ordering information device operating temperature range package shipping ? uc384xbdg t a = 0 to +70 c soic ? 14 (pb ? free) 55 units/rail uc384xbdr2g soic ? 14 (pb ? free) 2500 tape & reel uc384xbd1g soic ? 8 (pb ? free) 98 units/rail uc384xbd1r2g soic ? 8 (pb ? free) 2500 tape & reel uc384xbng pdip ? 8 (pb ? free) 50 units/rail uc284xbdg t a = ? 25 to +85 c soic ? 14 (pb ? free) 55 units/rail uc284xbdr2g soic ? 14 (pb ? free) 2500 tape & reel uc284xbd1g soic ? 8 (pb ? free) 98 units/rail uc284xbd1r2g soic ? 8 (pb ? free) 2500 tape & reel uc284xbng pdip ? 8 (pb ? free) 50 units/rail uc384xbvdg t a = ? 40 to +105 c soic ? 14 (pb ? free) 55 units/rail uc384xbvdr2g soic ? 14 (pb ? free) 2500 tape & reel uc384xbvd1g soic ? 8 (pb ? free) 98 units/rail uc384xbvd1r2g soic ? 8 (pb ? free) 2500 tape & reel uc384xbvng pdip ? 8 (pb ? free) 50 units/rail ncv3845bvd1r2g* t a = ? 40 to +125 c soic ? 8 (pb ? free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. x indicates either a 4 or 5 to define specific device part numbers. *ncv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable.
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 16 marking diagrams soic ? 14 d suffix case 751a soic ? 8 d1 suffix case 751 pdip ? 8 n suffix case 626 uc384xbvn awl yywwg 1 8 uc384xbvdg awlyww 1 14 384xb alywv 1 8 uc384xbn awl yywwg 1 8 uc284xbn awl yywwg 1 8 uc384xbdg awlyww 1 14 uc284xbdg awlyww 1 14 384xb alyw 1 8 284xb alyw 1 8 x = 4 or 5 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 17 package dimensions pdip ? 8 n suffix case 626 ? 05 issue n 14 5 8 b2 note 8 d b l a1 a eb e a top view c seating plane 0.010 ca side view end view end view with leads constrained dim min max inches a ???? 0.210 a1 0.015 ???? b 0.014 0.022 c 0.008 0.014 d 0.355 0.400 d1 0.005 ???? e 0.100 bsc e 0.300 0.325 m ???? 10 ??? 5.33 0.38 ??? 0.35 0.56 0.20 0.36 9.02 10.16 0.13 ??? 2.54 bsc 7.62 8.26 ??? 10 min max millimeters notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions a, a1 and l are measured with the pack- age seated in jedec seating plane gauge gs ? 3. 4. dimensions d, d1 and e1 do not include mold flash or protrusions. mold flash or protrusions are not to exceed 0.10 inch. 5. dimension e is measured at a point 0.015 below datum plane h with the leads constrained perpendicular to datum c. 6. dimension e3 is measured at the lead tips with the leads unconstrained. 7. datum plane h is coincident with the bottom of the leads, where the leads exit the body. 8. package contour is optional (rounded or square corners). e1 0.240 0.280 6.10 7.11 b2 eb ???? 0.430 ??? 10.92 0.060 typ 1.52 typ e1 m 8x c d1 b a2 0.115 0.195 2.92 4.95 l 0.115 0.150 2.92 3.81 h note 5 e e/2 a2 note 3 m b m note 6 m
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 18 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
uc3844b, uc3845b, uc2844b, uc2845b http://onsemi.com 19 package dimensions soic ? 14 case 751a ? 03 issue h notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 7.04 14x 0.58 14x 1.52 1.27 dimensions: millimeters 1 pitch soldering footprint 7x on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 uc3844b/d sensefet is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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